The invention relates to using determinism with a bus.
Referring to FIG. 1, a typical computer system 10 may include many devices that interact with a processor 20 (a central processing unit (CPU), as an example) of the system 10. For example, the processor 20 may write to a register of a bus device 14 by furnishing a write transaction to a host bus 12. However, the bus device 14 may not directly respond to transactions that appear on the host bus 12, but rather the bus device 14 may respond to transactions that appear on another bus 18 that is directly coupled to the bus device 14. For purposes of reproducing the write transaction on the bus 18, the computer system 10 may include a host bridge 16 that is coupled between the buses 12 and 18. The bridge 16 also completes the transaction on the host bus 12 based on the response provided by the bus device 14. The computer system 10 may include additional bridges to interface additional buses together, such as a bridge 22 that is coupled between the bus 18 and another bus 24, for example.
The transfer of the transaction from the host bridge to the bus device 14 may not be instantaneous, but rather, the bus 18 may skew the signals that represent the transaction to introduce a propagation delay. This delay may be a function of voltages and temperatures of the system 10 and may vary over time.
In some cases, it may be desirable to select how many clock cycles are required for data of the transaction to propagate along the bus 18 from the bridge 16 to core circuitry 17 of the bus device 14. For example, redundant subsystems (not shown) may be coupled to the bus 18, and as a result, for coherency reasons, it may be desirable for both subsystems to concurrently receive the same data in case one subsystem fails. As another example, the ability to predict the number of clock cycles may be helpful in debugging a bridge chip set.